1. Field of the Invention
The present invention relates to the structure of a ferroelectric memory cell, and a method of fabricating it, which particularly adapts to a highly integrated circuit.
2. Description of the Related Art
Generally, the flash memory is a type of nonvolatile memories, which, unlike SRAMs and DRAMs, do not lose their content when the power supply is cut off. It is also rewritable, but suffering short life due to a high voltage required for the writing. On the other hand, the ferroelectric random access memory (FRAM) has been developed to achieve the advantages of both RAM and flash memory, comprising a ferroelectric material which exhibits spontaneous electric polarization (separation of the center of positive and negative electric charge, making one side of the crystal positive and the opposite side negative) that can be reversed in direction by the application of an appropriate electric field. It may work with high speed at low voltage, and does not lose its content when the power supply is cut off.
Referring to FIG. 1 for illustrating an equivalent circuit of a conventional FRAM cell, it consists of an NMOS transistor TR1 and a capacitor C1. The gate of the NMOS transistor TR1 is connected with the word line WL, and the drain and source respectively with the bit line BL and one electrode of the capacitor C1. The other electrode of the capacitor C1 is connected with the plate line PL.
Referring to FIG. 2 for illustrating a cross sectional view of the FRAM cell, the NMOS transistor TR1 comprises the gate electrode 3 formed over a gate oxide layer 2 on a p-type silicon substrate 1 and the source and drain regions 4 and 5 self-aligned in the substrate 1. The ferroelectric capacitor C1 comprises a lower electrode 8 of Pt, a ferroelectric layer 9 of lead zirconate titanate (PZT) and an upper electrode 10 of Al, which are formed over an insulating layer 7 on a field oxide layer 6. The source region 4 is electrically connected with the upper electrode 10 via a contact hole 1. There is an insulating layer 13 formed over the transistor TR1 . In such conventional FRAM, the fact that the ferroelectric capacitor C1 is formed over the field oxide layer 6 causes restriction of the integrability of the ferroelectric memory cells. In order to resolve this problem, it has been proposed to form the capacitor in the active region in stead of the field oxide region, as shown in FIG. 3.
Referring to FIG. 3, the substrate 101 is divided by the field oxide layer 102 into active and non-active regions, including gate oxide layers 103 on which gate electrodes 104 are formed and enclosed by an insulating layer 105. At both sides of the gate electrodes 104 are formed the common drain region 106B and the source regions 106A, 106C to complete the MOS transistors. The common drain region 106B is connected with the bit line 107. The source regions 106A and 106C are electrically connected with the lower electrode 111 of the ferroelectric capacitor via a plug contact 109 formed of a polysilicon or tungsten in specific regions of a first insulating layer 108. The ferroelectric capacitor consists of the lower electrode 111, ferroelectric layer 112 and upper electrode 113. Then, deposited thereon is a second insulating layer 114, which is provided with contact holes to electrically connect the upper electrode 113 with the plate line 115. This serves to enhance the integrability of the memory cells because of the ferroelectric capacitors formed in the active regions. However, when annealing the ferroelectric layer deposited on the active regions in oxygen environment, oxygen molecules are diffused into the polysilicon or tungsten of the lower electrode 111 to form an oxide layer 110 between the lower electrode 111 and the upper surface of the plug contact 109. This results in cutting off the electrical connection between the lower electrode 111 and the plug contact 109, so that the voltage applied to the plate line 115 may be hardly transferred to the source region 106C. This causes the memory cells to malfunction.